Freescale Semiconductor /MKE14Z7 /SCG /LPFLLDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPFLLDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)LPFLLDIV1 0 (000)LPFLLDIV2

LPFLLDIV2=000, LPFLLDIV1=000

Description

Low Power FLL Divide Register

Fields

LPFLLDIV1

LPFLL Clock Divide 1

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

LPFLLDIV2

LPFLL Clock Divide 2

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

Links

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